1. Packaging
In a NAND flash chip, a single silicon wafer packaged inside is called a Die. A Die may internally be divided into two planes, each called a Plane. A Plane contains multiple Blocks, and each Block is further divided into multiple Pages.
Usually people do not concern themselves with the Die and Plane, but instead focus on things at the Block level and below.
The data of a single page is sometimes further divided into an upper half-page and a lower half-page, and each page carries a few extra bytes of storage space called the spare area. Some NAND flash management programs use the spare area to store management data, ECC check data, and so on.
Typically a block has 256, 1024, or 2048 pages.
A page usually has 512, 1024, 2048, etc. bytes.
2. Basic Operations of NAND Flash
The Block is the smallest unit of erasing, and the Page is the basic unit of reading and writing.
2.1 Erase
NAND flash is not like memory or a hard disk that can be rewritten in place. Once a bit on it (for SLC) is written to 1, it cannot be individually rewritten back to 0; instead it must be erased to 0 together with all the other bits in the Block it resides in.
2.2 Write
We say that the write operation of NAND flash is done in units of Pages, but in fact you can be precise down to the units within a Page. For example, you can first write bit 0 to 1, then write bit 1 to 1. But you cannot go back and write bit 0 to 0, because only an erase operation can change a bit that has been written to 1 back to 0.
2.3 Read
The basic unit of reading is said to be the Page. Of course you can also read just a few bits within a Page at a time, but the time taken is always the same.
3. Internal Structure of NAND Flash
The figure below shows the internal structure of one block of NAND flash; this image is a classic. As you can see, a Block is actually an array of transistors within the chip. A Page is a row or a part of a row of this array — that is, a single row may be further divided into multiple Pages.
WLx is the row-select line for row x. When WLx is at a high level, all the cells on the entire row (i.e., one Page) can be operated on. WL is the abbreviation for Word Line.
BLx is the bit-select line for bit x on a row. When a row WLx is selected, applying a high level to BLy allows a 1 to be written to the corresponding bit.
3.1 Internal Circuit Behavior During Read
In a typical NAND flash chip, a Block has a row of sense amplifiers connected to each bit line. When reading data, a row is first selected using Vread, and the word lines of the unselected rows are set to Vpass so that those transistors have conduction capability. Then the data on each cell of the selected row is read out by the sense amplifiers.
Voltages at various parts during a read operation
3.2 Internal Circuit Behavior During Write (Programming)
Programming is the process of writing a 1 to a cell. Likewise, the unselected rows are set to Vpass, the word line of the row to be selected is set to Vpgm, the selected bit line is set to GND, and the other bit lines are set to VDD.
Voltages at various parts during a write operation
That is:
3.3 Internal Circuit Behavior During Erase
Erase.
4. NAND Flash Does Not Support In-Place Update
A page of NAND flash, once written, can hardly be rewritten; only the whole block can be erased. If you want to change the data on a page, the common approach is not to erase the entire block and then rewrite everything after modifying it, but rather to mark the content of that page as invalid, write the modified data to a new page, and then update the pointer to point to the new page. This is a fundamental operation of the flash translation layer. The flash translation layer, abbreviated FTL, is a topic frequently studied in the industry.
nand flash page update(out-of-place update)
5. Comparison of SLC, MLC, and TLC
SLC = Single-Level Cell, i.e., 1 bit/cell, fast speed and long lifespan, extremely expensive (about 3 times or more the price of MLC), roughly 100,000 program/erase cycles of lifespan.
MLC = Multi-Level Cell, i.e., 2 bit/cell, average speed and average lifespan, average price, roughly 3,000–10,000 program/erase cycles of lifespan.
TLC = Trinary-Level Cell, i.e., 3 bit/cell, also called 8LC by some Flash manufacturers, slow speed and short lifespan, cheap price, roughly 500 program/erase cycles of lifespan; so far no manufacturer has been able to reach 1,000 cycles.
5.1 Speed Comparison
SLC is the fastest, and MLC is faster than TLC. But some sources also indicate that whether MLC is faster than TLC depends on the process node: TLC on a newer process is much faster than older MLC, though MLC’s lifespan is indeed a bit longer.
5.2 Program/Erase Cycle Comparison
The fact that a “TLC chip” can only be written 500 times does NOT mean that a USB drive is done after being plugged/unplugged 500 times! As a simple example, suppose you have an 8 GB USB drive; writing 8 GB into it counts as one time; clearing it and writing 3 GB counts as the second time, and clearing it again and writing 5 GB still counts as the second time; writing another 1 GB then starts counting as the third time.
Looked at from another angle, suppose an 8 GB USB drive can only be program/erased 500 times in its lifetime, then in theory this USB drive can load 4,000 GB of files over its lifetime. And an MLC-chip USB drive can load at least 24,000 GB to 80,000 GB over its lifetime. This is why TLC-chip USB drives are said to be relatively short-lived.
About TLC:
The TLC chip technology of the X3 (3-bit-per-cell) architecture is an extension of MLC and TLC technology. The earliest NAND Flash technology architecture was SLC (Single-Level Cell), whose principle is to store 1 bit of data in one memory storage cell, until MLC (Multi-Level Cell) technology took over and the architecture evolved to store 2 bits per memory storage cell.
In 2009, the TLC architecture was formally launched, representing one memory storage cell able to store 3 bits, further reducing cost substantially.
Just like the previous wave of the SLC-to-MLC technology trend, this time it was also NAND Flash giant Toshiba that ignited the battle, after which Samsung Electronics rushed to join the fray, causing the entire TLC technology to be mass-produced in large quantities and applied in end products.
Although TLC chips have larger storage capacity and much lower cost, their performance is also greatly reduced, so they can only be used in low-end NAND Flash-related products, such as low-speed flash memory cards, small memory cards like microSD, or flash drives.
For applications with high technical thresholds — such as embedded applications, smartphones, and solid-state drives (SSDs) — that demand high speed and error-free performance from NAND Flash, SLC or MLC chips must be used.
In 2010, the main growth drivers of the NAND Flash market came from smartphones and tablet computers, both of which had to use SLC or MLC chips, so both types of chips were in a shortage state, while TLC chips were continuously oversupplied and dragged down the average price of the entire industry, so that when market research firm iSuppli tallied the global NAND Flash output value for the second quarter of 2010, a rare market-shrinkage situation occurred, dropping from 4.3 billion US dollars in the first quarter of 2010 to 4.1 billion US dollars, a decrease of 6.5%.
6. ECC, Bad Blocks, and Wear Leveling
Because the cells of NAND flash have a limited number of program/erase cycles, after many uses a certain cell may no longer be erasable and unable to be written with correct data. At this point, the block is called a bad block.
When software uses NAND flash, it needs to manage these bad blocks, record the bad blocks, and avoid them when writing data later.
When software uses NAND flash, it also needs to take care to distribute erase operations across different blocks as much as possible. This can reduce the occurrence of bad blocks (until all blocks are close to failing together). This behavior is called wear leveling.
You cannot predict which cell of which block will fail at what time, so ECC check data is usually written to the spare area at the same time data is written, so that when a certain bad cell first fails it can be detected and the data recovered.
7. References
1. Understanding Flash: Blocks, Pages and Program / Erases
2. SD Knowledge — About Flash Memory Chips SLC, MLC, and TLC
3. Nand Flash Basic Introduction
4. Sense Amplifier for Flash Memories: Architectural
Exploration and Optimal Solution
5. MODELING THE PHYSICAL CHARACTERISTICS
OF NAND FLASH MEMORY
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