Semiconductor

Understanding Low-Level Principles – Memory Series | S06 | How DDR5 Doubles Memory Bandwidth Compared to DDR4 Key Insight: Every new generation of memory standard is essentially bargaining with the laws of physics — when bandwidth is insufficient, find a new way to “squeeze” more data through. 1. The Bandwidth Improvement Formula Memory bandwidth calculation... » read more

S08 — How Does an Address Travel from the CPU to a DRAM Cell Key Insight: Every bit of data has its complete journey map. The Complete Path from CPU to DRAM How does an address issued by the CPU ultimately select a DRAM cell? It requires a complete address resolution process. Complete path (simplified):... » read more

S03 — With DRAM, Why Does the CPU Still Need Cache? How Multiple Cache Levels Work Together Key Insight: The biggest bottleneck in the bucket often determines the ceiling of your effort. The Speed Chasm Between CPU and Memory Modern CPUs are extremely powerful at computation, but accessing memory is painfully slow: Performance gap (typical... » read more

S09 — ECC Memory: How Single-Bit Errors Are Detected and Corrected Key Insight: A reliable system is one that can still operate correctly under the worst conditions. Two Types of Memory Errors: Error Detection vs. Error Correction Memory errors fall into two categories: Bit Flip: Physical causes: - Cosmic rays (high-energy particles) hitting a DRAM... » read more

S10 — How to Read a Memory Datasheet Key Insight: Engineers who can read a datasheet can make correct product decisions. Basic Structure of a Datasheet A memory datasheet typically contains the following main sections: Typical memory datasheet structure: 1. Overview - Capacity, model number, voltage, package 2. Architecture - Organization (e.g., 1G × 8,... » read more

Understanding Low-Level Principles – Memory Series | S04 | Complete DRAM Access Timing: Commands, Signals, and the Source of Latency Key Insight: The journey of data from Cell to CPU core is etched in every step on the timing diagram. Read the timing diagram, and you’ve read half of DRAM. 1. DRAM Command and Signal... » read more

S01 — DRAM: How One Capacitor and One Transistor Store One Bit Key Insight: Behind complex systems, there are often just a few simple physical principles at work. Understanding DRAM starts with the most fundamental Cell. 1. Physical Structure of a DRAM Cell 1.1 What Is DRAM DRAM (Dynamic Random Access Memory) is the main... » read more

S02 — Why Does DRAM Need “Refresh”? The Essential Difference Between SRAM and DRAM Key Insight: SRAM latches data with transistors, DRAM stores data with capacitors — one remembers forever as long as power is on, the other must periodically “recharge” to retain data. 1. The Essence of the DRAM Refresh Problem 1.1 Physics of... » read more

Understanding Low-Level Principles – Memory Series | S05 | Bank, Row, Column — How a Memory Address is Step-by-Step Mapped to a Specific Cell Key Insight: Translating an address into a physical access requires many layers of abstraction. Understanding Bank internal structure is the key to understanding DDR performance. 1. DRAM Chip Internal Structure: The... » read more

S07 — Why the Memory’s Rated Frequency Is Not Its Actual Working Frequency Key Insight: The name and the substance are never the same thing. The Secret Hidden in DDR’s Name When buying memory, you see labels like “DDR5-4800”. What does the number 4800 represent? DDR5-4800 meaning: 4800 = 4800 MT/s = 4800 Mega Transfers... » read more