Hardware

H05 — What Happens After RAM Powers On: SPD Chips and BIOS Memory Training Key insight: Every RAM stick works normally in a computer because, in the instant of booting, someone does a lot of calibration work behind the scenes. SPD Chip: The RAM’s “ID Card” Every RAM module has an SPD (Serial Presence Detect)... » read more

H01 — How Memory Modules Plug Into the Motherboard: DIMM Structure and Socket Design Key Insight: Behind every visible interface lie countless electrical conventions. DIMM Full Name and Basic Concepts DIMM = Dual Inline Memory Module. DIMM vs SIMM： SIMM（Single Inline Memory Module）： - 单面引脚（只能接触一侧的触点） - 72-pin 或 30-pin（早期） - 只能提供 32-bit 或 16-bit 数据宽度... » read more

H04 — XMP and EXPO: How Memory Overclocking Works, and Why a 3200-rated Stick Can Run at 3600 Key Insight: Bought a 3200-rated stick, runs at 3600. It’s not magic; it’s engineering. Why Memory Has Both JEDEC and XMP Frequencies When buying memory, you see DDR4-3200 on the specs, but you can actually set it... » read more

H08 — DDR5 On-Die ECC and Sideband ECC: On-Chip Error Correction vs System ECC Key Insight: ECC is not just a technology. It is a commitment to data reliability. ECC Types Introduced in DDR5 DDR5 has three types of ECC, working at different levels: DDR5 ECC 的三层架构： Layer 1：On-Die ECC（片内 ECC） → DRAM 颗粒内部，每颗颗粒自己纠错 →... » read more

H07 — How DDR Power Consumption Is Calculated: IDD Parameters and Power Models Key Insight: Every refresh, every activation, every read and write consumes power. Components of DDR Power Consumption DDR memory power consumption has three parts: Static Power (Leakage) + Dynamic Power (Switching) + I/O Power. DDR 系统功耗分解： 1. 核心功耗（Core Power）： - DRAM Cell... » read more

H03 — CL-tRCD-tRP-tRAS: How Memory Timings Affect Actual Latency Key Insight: Choosing memory only by rated frequency is like buying a car only by top speed. You’ll miss a lot. What Are Memory Timings Memory timings are parameters describing delays between memory commands. They collectively determine how fast memory operations are. DDR4 主要时序参数（以 DDR4-3200 CL22... » read more

H10 — The Memory Controller Inside the CPU: IMC Architecture and Core Interaction Key Insight: The best memory control makes the CPU unaware of latency. Location of the Memory Controller (IMC) The Memory Controller is the bridge between the CPU and DRAM. Modern CPUs integrate the IMC on the CPU die. CPU 芯片架构（以 Intel Skylake... » read more

H06 — How Memory Module Gold Fingers Are Connected: PCB Traces, Impedance Control, and DQ Signal Integrity Key Insight: Invisible trace lengths determine visible system stability. Memory PCB Structure A memory module (DDR DIMM) is an independent PCB filled with signal traces and power planes. DDR4 UDIMM PCB 结构（6 层或 8 层）： Layers： Layer 1（Top）：信号层，元器件和... » read more

H02 — Why Memory Should Be Installed in Pairs: How Dual Channel Works Key Insight: A single tree does not make a forest. Neither does a single channel for bandwidth. Single Channel vs Dual Channel: Numerical Comparison What is the performance difference between one 16 GB DDR4-3200 stick and two 8 GB DDR4-3200 sticks? 理论带宽对比：... » read more

H09 — How Memory Modules Are Manufactured: PCB, Soldering, and Testing Key Insight: Behind every reliably working memory module is a strict quality screening. Memory Module Manufacturing Flow The complete flow from components to finished memory module: 内存条制造流程： 1. PCB 生产 - 采购空白 PCB（6~8 层，DDR4/DDR5 规格） - 沉金（ENIG）表面处理（金手指镀金） - 丝印（Silkscreen）印刷 2. 零件准备 - DRAM 颗粒：按频率/品质分级（三星... » read more