title: [Writing an OS Kernel from Scratch] 337 – DRAM Training: From Principles to Debugging
category: os
tag: [dram, ddr, embedded, signal-integrity]
source: https://github.com/golang12306/os-kernel-from-scratch
[Writing an OS Kernel from Scratch] 337 – DRAM Training: From Principles to Debugging
1. What Is DRAM Training?
DRAM Training is the process where the DDR controller automatically adjusts signal parameters during initialization, aiming to accurately sample at the center of the data eye diagram, preventing read/write errors.
Analogy: When a USB Type-C cable is plugged into a laptop, the laptop first detects the CC line’s impedance and negotiates the power profile. DDR Training is the “handshake negotiation” between the CPU/SoC and DDR, except it negotiates timing parameters.
┌─────────────────────────────────────────────────────────────┐
│ DRAM Training Core Problem │
├─────────────────────────────────────────────────────────────┤
│ │
│ DDR signal transmission diagram: │
│ │
│ DQ[0] ──────────────────────► ───────────────── DQ[0] │
│ ──►Data Valid Window◄── │
│ DQS ──► ──────────────────────► ─────────────── DQS │
│ ▲ ▲ │
│ │ │ │
│ Rising edge Rising edge │
│ │
│ Problem: │
│ 1. Data arrival time is inconsistent (fly-by vs direct topology)│
│ 2. DQS and DQ skew drifts with temperature │
│ 3. Signal reflections cause eye closure │
│ 4. DDR chip characteristics vary (even within the same batch)│
│ │
│ Solution: Controller dynamically adjusts each DQ's delay │
│ to find the optimal sampling point │
│ │
└─────────────────────────────────────────────────────────────┘2. DDR Signal Integrity Basics
2.1 Key Timing Parameters
DDR signals involve multiple timing parameters. Understanding them is the foundation for understanding Training:
┌─────────────────────────────────────────────────────────────┐
│ DDR3 Read Timing (simplified) │
│ │
│ CLK ─┐ ─┐ ─┐ ─┐ ─┐ ─┐ ─┐ ─┐ ─┐ │
│ └──┘ └──┘ └──┘ └──┘ └──┘ └──┘ └──┘ │
│ │
│ Command ───────────[READ]────────────────────────── │
│ │
│ DQS ───────────────────────┐ ┌───┐ ┌───┐ │
│ └────┘ └────┘ └────│
│ │
│ DQ ───────────────────────────[Data Valid Window]── │
│ <------ tDQSCK ----> │
│ <---- tAC ----> │
│ │
│ tDQSCK: DQS output access time from CK │
│ tAC: Data output access time from DQS │
│ tDQSQ: DQS-DQ skew (within a group) │
│ tQH: DQS-DQ hold time factor │
│ │
└─────────────────────────────────────────────────────────────┘3. Training Steps
Complete DRAM Training sequence:
1. VREF Training (Voltage Reference Training):
- Find the optimal Bit Line voltage reference level
- Typically VREF = VDDQ/2 = 0.6V (for DDR4)
- Adjust VREF to find the widest voltage margin
2. ZQ Calibration (Impedance Calibration):
- Calibrate output driver impedance
- Calibrate ODT (On-Die Termination) resistance
- Target: 240Ω ± 10%
3. Write Leveling:
- Align DQS with CK for write operations
- Compensate for fly-by topology delays
- Adjust each chip's DQS delay independently
4. Read DQ/DQS Training (Gate Training):
- Align DQS with DQ for read operations
- Find the DQS sampling window
- Adjust delay to center DQS in the DQ valid window
5. Read DQ Bit Deskew:
- Fine-tune each DQ bit's delay individually
- Compensate for PCB trace length differences
- Ensure all bits arrive simultaneously
6. Write DQ Bit Deskew:
- Fine-tune each DQ bit's delay for writes
- Ensure data setup and hold times are met
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