Understanding Low-Level Principles – Memory Series | S04 | Complete DRAM Access Timing: Commands, Signals, and the Source of Latency
Key Insight: The journey of data from Cell to CPU core is etched in every step on the timing diagram. Read the timing diagram, and you’ve read half of DRAM.
1. DRAM Command and Signal Overview
1.1 DDR Chip Command Interface
DDR chips receive commands through a set of parallel signals. Each command is sampled on the clock rising edge (or both edges):
DDR4 chip command signals (CS, RAS, CAS, WE, CKE, ODT):
CS# (Chip Select) : Chip select, DRAM receives commands when low
RAS# (Row Address Strobe): Row address strobe, low = "row-related command"
CAS# (Column Address Strobe): Column address strobe, low = "column-related command"
WE# (Write Enable) : Write enable, low = "write command"
CKE (Clock Enable) : Clock enable, controls whether clock signal is active
ODT (On-Die Termination): On-die termination resistor for signal integrity
Command encoding (CS# + RAS# + CAS# + WE#):
ACT = (0, 0, 1, 1) ← Row Activate
READ = (0, 1, 0, 1) ← Column read command
WRITE = (0, 1, 0, 0) ← Column write command
PRE = (0, 0, 1, 0) ← Precharge (close current row)
REF = (0, 0, 0, 1) ← Refresh
MRS = (0, 0, 0, 0) ← Mode Register Set (configuration)
NOP = (0, 1, 1, 1) ← No Operation
Address signals (A[17:0]):
- Row address when transmitting row address (for ACT)
- Column address when transmitting column address (for READ/WRITE)
Bank address (BA[2:0]):
- Selects one of 8 Banks
Command valid condition: CS# must be low1.2 Clock and Data Signals
DDR clock and data signals:
CK/CK# (Clock): Differential clock, DDR sampling edge
- DDR1: Samples only on CK rising edge (SDR)
- DDR2/DDR3/DDR4: Samples on both CK rising and falling edges (DDR)
- CK frequency = half of actual data transfer rate
DQS/DQS# (Data Strobe): Data strobe signal
- Read operation: Driven by DRAM, edges aligned with data
- Write operation: Driven by memory controller, edges aligned with data
- Receiver uses DQS to sample DQ data (same principle as DDR clock)
DQ (Data): Data signals, x8 chip = 8 lines
DM/DBI (Data Mask / Data Bus Inversion):
- DM: Write data mask, used for partial writes
- DBI: Data bus inversion flag, used for power reduction
Command timing example (ACT → READ → PRE):
Cycle: 0 1 2 3 4 5 6 7 8 ...
CK ─┐ ─┐ ─┐ ─┐ ─┐ ─┐ ─┐ ─┐ ─┐ ─┐
└ ─┘ ─┘ ─┘ ─┘ ─┘ ─┘ ─┘ ─┘ ─┘
CS# ─┐ ─┐
└────────────────────────────────────┘ └
RAS# ─┐ ──────────────────────────── ─┐
└┘ │ └┘
CAS# ──────────────────────────────────────┐ ─┐
┘ └┘
WE# ──────────────────────────────────────────────────────────
DQ ──────────────────────────────────────[Data Out]───2. Key Timing Parameters
DDR4 core timing parameters (at DDR4-3200):
tRCD (RAS to CAS Delay):
ACT command → READ/WRITE command minimum interval
tRCD = 13.75ns (22 cycles at 3200 MT/s)
Determines row activation to column access latency
tCL (CAS Latency):
READ command → first data on DQ pins
tCL = 13.75ns (22 cycles)
The most well-known memory timing parameter
tRP (Row Precharge Time):
PRE command → next ACT command minimum interval
tRP = 13.75ns (22 cycles)
Close current row, open a new row
tRAS (Row Active Time):
ACT command → PRE command minimum interval
tRAS = 32ns (varies by spec)
How long a row must remain active
tRFC (Refresh Cycle Time):
REF command duration
tRFC = 350ns (DDR4-8Gb)
Longest single timing parameter
tCCD (Column to Column Delay):
Two consecutive READ/WRITE commands minimum interval
tCCD = 4 cycles (DDR4)
Determines maximum burst throughputLatency breakdown (DDR4-3200):
CPU → Memory Controller: ~20ns (on-die)
Controller → DRAM: ~14ns (tRCD, row activation)
DRAM cell access: ~14ns (tCL, column read)
Data return: ~12ns (data transfer on bus)
Total: ~60ns (≈ 200 CPU cycles at 3.5GHz)
Memory bandwidth utilization considerations:
- Sequential access: high utilization (prefetch, page hit)
- Random access: low utilization (page miss, need tRCD+tRP+tCL per request)
- Real workloads typically achieve 60-80% of theoretical bandwidth
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