S01 — DRAM: How One Capacitor and One Transistor Store One Bit
Key Insight: Behind complex systems, there are often just a few simple physical principles at work. Understanding DRAM starts with the most fundamental Cell.
1. Physical Structure of a DRAM Cell
1.1 What Is DRAM
DRAM (Dynamic Random Access Memory) is the main memory of virtually all general-purpose computing devices. From phones to servers, from PCs to supercomputers, DDR SDRAM is synonymous with main memory.
Core characteristics of DRAM:
- Volatile: Data is lost when power is off
- Random access by address: Access latency is the same for any address (unlike SSD block access)
- Each bit is stored by charging/discharging a capacitor: Extremely high density
1.2 Circuit Structure of One DRAM Cell
A DRAM Cell consists of only two components:
WL (Word Line)
│
───────┤ NMOS T (Transistor, Switch)
│
├───┬────────────── BL (Bit Line)
│
────┴─────
████ ← Storage Capacitor
───────── Charge → 1, No charge → 0
│
GND
Two ports:
- WL (Word Line): Controls transistor on/off, driven by row decoder
- BL (Bit Line): Data line for reading/writing data, connected to sense amplifier
One Cell = 1 NMOS + 1 Capacitor1.3 Principle of Capacitor Charge Storage
Basic capacitor structure: two conductors separated by an insulator
┌──────────┐
────│ Plate A │──────── Conductor (connected to circuit)
│ ↓↓↓ │
│ Insulator│
│ ↑↑↑ │
└──────────┘
────│ Plate B │──────── Conductor (connected to circuit)
└──────────┘
Charge stored in capacitor: Q = C × V
C: Capacitance (determined by area and insulator thickness)
V: Voltage
In DRAM:
- "Store 1": Capacitor charged to VDD, charge Q1
- "Store 0": Capacitor discharged to 0V, charge Q0
Charging = Writing "1"
Discharging = Writing "0"
Detecting voltage change = Reading2. Bit Line and Word Line: How Cells Are Accessed
2.1 Bit Line (BL)
Each DRAM Cell does not connect directly to the amplifier, but through a shared Bit Line (BL).
A Bit Line connects multiple Cells (typically 256~512):
BL (Bit Line, shared)
│
Cell 0 ──┤ ├── Cell 1 ──┤ ├── Cell 2 ──┤ ...
│ │ │
WL0 WL1 WL2
Word Line controls which Cell connects to BL
At any given time, only one Cell per BL is connected
BL voltage is detected by the Sense Amplifier.2.2 Word Line (WL)
The Word Line determines which Cell is selected to connect to the Bit Line.
Word Line operation:
WL=0 (Not selected):
→ NMOS cut off
→ Cell disconnected from BL
→ Cell charge remains unchanged (static retention)
WL=1 (Selected):
→ NMOS conducts
→ Cell's capacitor connected to BL
→ Can read or write charge
Row activation (ACT command):
Memory controller sends Row Address
→ Row decoder pulls the corresponding WL high
→ All cells in that row connect to their respective BLs
→ Sense amplifier detects each cell's charge state3. Sense Amplifier: How to Read a Tiny Voltage Change
Sense amplifier circuit schematic:
┌─────────────────────────────────┐
│ │
│ VDD │
│ │ │
│ ──┴── │
│ │ │ │
│ │ P1 │ P2 │
│ │ │ │
│ ├─────┼─────── BL │
│ │ │ │
│ │ N1 │ N2 │
│ │ │ │
│ ──┬── │
│ │ │
│ GND │
│ │
│ BL_REF (reference voltage) │
└─────────────────────────────────┘
Principle:
1. Before reading: precharge BL to VDD/2
2. When Cell connects: charge sharing occurs
- If Cell stores "1": BL voltage rises slightly (ΔV)
- If Cell stores "0": BL voltage drops slightly (-ΔV)
3. ΔV is very small (~100-200mV, 1% of VDD)
4. Sense amplifier amplifies this ΔV to full VDD or GND4. Read/Write Process
Read operation (full cycle):
Step 1: Precharge
→ Set BL voltage = VDD/2 (reference level)
→ Close all WLs (no cells connected)
Step 2: Row Activation (ACT)
→ Row decoder selects the target row
→ WL goes high, all cells in this row connect to BLs
→ Each Cell shares charge with its BL
→ Sense amplifier detects and amplifies
Step 3: Column Read (READ)
→ Column decoder selects the target column
→ Data from the selected cell appears on DQ pins
→ tRCD (RAS to CAS Delay) must elapse between ACT and READ
Step 4: Restore (destructive read)
→ Reading a DRAM cell destroys its charge
→ Must write back the amplified value immediately
→ The sense amplifier itself completes the write-back
Step 5: Precharge (PRE)
→ Close the current row (all WLs go low)
→ Prepare for next row activation5. Density and Capacity Evolution
DRAM process technology evolution:
Generation Year Process Capacity per die VDD
1st Gen 1970 10 µm 1 Kb 12V
DDR 1998 0.18 µm 64 Mb 2.5V
DDR2 2003 90 nm 256 Mb 1.8V
DDR3 2007 50 nm 1 Gb 1.5V
DDR4 2014 20 nm 8 Gb 1.2V
DDR5 2020 14 nm 16 Gb 1.1V
DDR6 2026? 7 nm? 32 Gb? <1.0V
Higher density, lower voltage, faster speed — the trend of each generation
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