Physical causes of capacitor leakage:

  - There is an insulating layer (SiO₂ or high-k material) between the capacitor plates
  - The insulator is not a perfect barrier; there is always a small tunneling current (quantum tunneling)
  - Higher temperature increases carrier kinetic energy, raising tunneling probability
  - At 25°C: Data retention time ≈ 64ms
  - At 60°C: Leakage rate increases ~4×, retention time drops to ~16ms

Capacitor voltage decay process:
  - Fully charged (storing "1") → VDD ≈ 1.2V
  - Leakage → voltage slowly drops
  - Drops below the Sense Amplifier threshold (~0.6V = VDD/2)
  → "1" is misread as "0" → Data corruption

Conclusion: Data must be read back and rewritten before the capacitor voltage drops below threshold
  → This is "Refresh"

Refresh is not simply "read everything" — it is a precise row-by-row operation:

Step 1: Memory controller sends REF command
  → Specifies target Bank (REF# Bank)

Step 2: Bank's internal row decoder activates a row
  → All cells in that row (1024~8192) simultaneously connect to their Bit Lines

Step 3: Sense Amplifier reads the entire row's data
  → Amplifies each cell's tiny voltage change to full logic levels
  → Determines whether each cell is "1" or "0"

Step 4: Immediate write-back (Restore)
  → The amplified data directly recharges the capacitors
  → Capacitors restored to VDD ("1") or GND ("0")

Step 5: Precharge
  → Close the row, prepare for the next refresh cycle

Note: During refresh, that Bank cannot respond to normal read/write requests.

DDR4 refresh parameters (JEDEC JESD79-4B):

Refresh Interval (tREFI):
  → Standard value: 7.8125µs (typical refresh interval)
  → 64ms / 7.8125µs = 8192 refreshes per 64ms
  → A refresh command must be issued every 7.8µs

Refresh Cycle Time (tRFC):
  → Refreshing one row takes ~350ns (DDR4-8Gb)
  → Total time to refresh 8192 rows ≈ 8192 × 350ns ≈ 2.87ms
  → Duty cycle = 2.87ms / 64ms ≈ 4.5%

During this 4.5% of the time, DRAM is inaccessible — this is DRAM's inherent overhead.

Three refresh rate tiers (JEDEC DDR4):

1x Refresh (Standard):
  - Refresh all rows once per 64ms
  - tREFI = 7.8125µs
  - Used for: room temperature (< 85°C) environments

2x Refresh (High-temperature compensation):
  - Refresh all rows twice per 64ms (half the interval)
  - tREFI = 3.9µs
  - Used for: high-temperature environments (85°C ~ 105°C)
  - DDR4 chips switch internally, no software intervention needed

4x Refresh (Extreme high temperature):
  - Refresh all rows four times per 64ms
  - tREFI = 1.95µs
  - Used for: sustained high temperature (> 105°C) or maximum data reliability

Mobile/automotive DRAM may use even denser refresh (8x).

Refresh blocks the Bank, reducing effective bandwidth:

Scenario: GPU continuously accessing video memory (high bandwidth demand)

DDR4-3200, 4.5% refresh overhead:
  - Nominal bandwidth = 25.6 GB/s (64-bit channel)
  - Actual available bandwidth ≈ 25.6 × (1 - 4.5%) ≈ 24.4 GB/s
  - Loss of about 1.2 GB/s

Refresh also causes latency jitter (latency spikes):
  - High-priority requests may be delayed by an ongoing refresh
  - Worst-case: a request arriving just as refresh starts
  - Must wait for the entire tRFC (~350ns) to complete
  - For real-time systems, this 350ns jitter can be significant

SRAM vs DRAM comparison:

                 SRAM                    DRAM
Storage element   6 transistors (6T)      1 transistor + 1 capacitor
Per bit area      Large (120~200 F²)      Small (6~8 F²)
Density            Low                     High (6~10× denser)
Speed              Fast (~1ns)            Slow (~10-50ns)
Power              Higher (leakage)       Lower (but needs refresh)
Cost per bit       High                    Low
Need refresh?      No                      Yes (every 64ms)
Volatility         Volatile                Volatile

SRAM cell (6T):
      VDD
       │
  ┌────┴────┐
  │         │
  └──┬──┬───┘
     │  │
  ┌──┴──┴───┐        ┌──┴──┴───┐
  │         │        │         │
  │  INV1   │────────│  INV2   │
  │         │        │         │
  └──┬──┬───┘        └──┬──┬───┘
     │  │               │  │
  ┌──┴──┴───┐        ┌──┴──┴───┐
  │  N1     │        │  N2     │
  └─────────┘        └─────────┘
     │                   │
    BL                  BL#
  (bit line)         (bit line bar)

  Two cross-coupled inverters (latch)
  Data is held by positive feedback — as long as power is on,
  the data is stable without any refresh.