Organization hierarchy of a DRAM chip (Die):

Smallest unit: DRAM Cell (1 NMOS + 1 Capacitor) = 1 bit
         ↓
Multiple cells form a Row: each row shares the same Word Line
         ↓
Multiple rows form a Subarray:
  - Typically 256~512 rows × 1024 columns
  - Has its own local Sense Amplifier
         ↓
Multiple Subarrays form an Array
         ↓
Multiple Arrays form a Bank
  - Has its own Row Decoder and Column Decoder
  - Can independently accept ACT/READ/WRITE/PRE commands

Internal structure of a DDR4 x8 chip (8Gb capacity):
  32 Arrays × each Array has 256 rows × 1024 columns
  → Total: 32 × 256 × 1024 = 8,388,608 cells (8Mb, larger with multiple banks)
  → Plus Bank structure, Bank Group (DDR5), I/O interface → complete chip

Internal structure of a Bank (DDR4, simplified diagram):

              Row Decoder
                    │
  Word Line 0 ──────┤
  Word Line 1 ──────┤
  Word Line 2 ──────┤
  ...
  Word Line N ──────┤
                    │
  ┌──────────────────────────────────────────────┐
  │           Bit Lines run vertically            │
  │                                             │
  │  Cell[0,0]  Cell[0,1]  Cell[0,2] ... Cell[0,1023]  ← Row 0
  │    │          │          │              │
  │  Cell[1,0]  Cell[1,1]  Cell[1,2] ... Cell[1,1023]  ← Row 1
  │    │          │          │              │
  │  Cell[2,0]  Cell[2,1]  Cell[2,2] ... Cell[2,1023]  ← Row 2
  │    │          │          │              │
  │   ...        ...        ...            ...     ← ...
  │    │          │          │              │
  │  Cell[N,0]  Cell[N,1]  Cell[N,2] ... Cell[N,1023] ← Row N
  │                                             │
  └──────────────────────────────────────────────┘
                    │
              Sense Amplifiers (column direction)
                    │
              Column Mux
                    │
                   IO

Each intersection (Cell): one Word Line + one Bit Line + NMOS + Capacitor

Physical address to DRAM address mapping (simplified):

Physical Address (PA) [48 bits]:
  PA[47:36] → unused/reserved
  PA[35:30] → Channel selection
  PA[29]    → Rank selection (dual-rank DIMM)
  PA[28:18] → Row address (11 bits, 2048 rows)
  PA[17:12] → Bank address (6 bits, 64 banks)
  PA[11:6]  → Column address (6 bits, 64 columns)
  PA[5:0]   → Byte within Cache Line (64 bytes = 6 bits)

After address mapping:
  ┌─────────┬─────────┬──────┬───────┬──────┐
  │ Channel │  Rank   │ Row  │ Bank  │ Col  │
  ├─────────┼─────────┼──────┼───────┼──────┤
  │   2     │   1     │  11  │   6   │  6   │
  └─────────┴─────────┴──────┴───────┴──────┘

  Total bits: 2+1+11+6+6 = 26 bits → 64MB addressable per rank

  Note: Actual mapping varies by memory controller and motherboard

Row Buffer concept:

  DRAM reads an entire row at once into the row buffer (Sense Amplifiers)
  = "Opening a Page" (page = row size, typically 1KB~8KB)

  ┌─────────────────────────────────────────────────┐
  │                   DRAM Bank                      │
  │                                                  │
  │  ┌─────────────────────────────────────────────┐ │
  │  │  Row 0                                       │ │
  │  │  Row 1                                       │ │
  │  │  ...                                         │ │
  │  │  Row N                                       │ │
  │  └─────────────────────────────────────────────┘ │
  │                    │                              │
  │  ┌─────────────────▼───────────────────────────┐ │
  │  │         Row Buffer (Sense Amplifiers)        │ │
  │  │  (Holds one row of data, acts as cache)      │ │
  │  └─────────────────────────────────────────────┘ │
  │                    │                              │
  │                  I/O                              │
  └──────────────────────────────────────────────────┘

  Page Hit:  Requested Row is already in Row Buffer
    → Only need Column access (tCL) — fast, ~14ns

  Page Miss: Requested Row is different from the one in Row Buffer
    → PRE close current row (tRP)
    → ACT open new row (tRCD)
    → Column access (tCL)
    → Total: ~42ns — 3× slower than Page Hit

  Page Empty/Closed: No row in Row Buffer (just powered up)
    → ACT open row (tRCD)
    → Column access (tCL)
    → Total: ~28ns

Page Hit/Miss impact on bandwidth:

  Random access pattern (worst case):
    Each access causes Page Miss
    ≈ 42ns per access → effective bandwidth ≈ 1.5 GB/s (DDR4-3200)

  Sequential access pattern (best case):
    Each access is Page Hit
    ≈ 14ns per access → effective bandwidth ≈ 22 GB/s (DDR4-3200)

  Conclusion:
    - Sequential access bandwidth ≈ 15× random access bandwidth
    - Memory controller uses address mapping to improve page hit rate
    - Linux huge pages (2MB/1GB) reduce TLB misses and improve spatial locality