S07 — Why the Memory’s Rated Frequency Is Not Its Actual Working Frequency
Key Insight: The name and the substance are never the same thing.
The Secret Hidden in DDR’s Name
When buying memory, you see labels like “DDR5-4800”. What does the number 4800 represent?
DDR5-4800 meaning:
4800 = 4800 MT/s = 4800 Mega Transfers per second
= 4.8 billion data transfers per second
But this refers to the I/O signal transfer rate (Transfer Rate),
NOT the actual operating frequency of the memory core (Core Frequency).
What is the actual internal clock frequency of the DRAM core?
DDR5 core frequency = 4800 / 2 / 2 = 1200 MHz
Why divide by 2? Because DDR is Double Data Rate, transferring on both edges
Divide by 2 again because DDR5 uses 2 clock domains (half clock frequency)DDR stands for: Double Data Rate — data is transferred on both the rising and falling edges of the clock, hence “double data rate.”
Frequency Conversion Table
DDR1 / DDR2 / DDR3 / DDR4 / DDR5 frequency comparison:
DDR4-2400:
Rated frequency: 2400 MT/s
I/O clock: 1200 MHz (one transfer each rising/falling edge = 2400 MT/s)
Core frequency: 600 MHz (internal frequency is lower)
DDR4-3200:
Rated frequency: 3200 MT/s
I/O clock: 1600 MHz
Core frequency: 800 MHz
DDR5-4800:
Rated frequency: 4800 MT/s
I/O clock: 2400 MHz (DDR5 has two half-speed clocks, 2400/1200)
Core frequency: 1200 MHz
DDR5-6400:
Rated frequency: 6400 MT/s
I/O clock: 3200 MHz
Core frequency: 1600 MHzWhy DDR Is “Double” Data Rate
Essential difference between DDR and SDR (Single Data Rate):
SDR (one transfer per clock rising edge):
┌───┐ ┌───┐ ┌───┐
│ │ │ │ │ │ Clock cycle = 10ns
└─┬─┘ └─┬─┘ └─┬─┘
│ │ │
DataA DataB DataC
1 transfer / 10ns = 100 MT/s = 100 MHz bandwidth
DDR (transfers on both rising and falling edges):
┌───┐ ┌───┐ ┌───┐
│ │ │ │ │ │ Clock cycle = 10ns
└─┬─┘ └─┬─┘ └─┬─┘
│ │ │
DataA1 DataA2 DataB1 DataB2 ...
2 transfers / 10ns = 200 MT/s = 200 MHz bandwidth
With the same 100MHz external clock, DDR bandwidth is 2× SDR.Effective Frequency vs. Actual Frequency
In memory bandwidth calculations, the commonly used “effective frequency” is the DDR data transfer rate:
DDR5-4800 bandwidth calculation:
Data width: 64 bit (single channel)
Transfer rate: 4800 MT/s (4.8 billion transfers per second)
Each transfer: 64 bit = 8 bytes
Bandwidth = 4800 MT/s × 8 bytes = 38.4 GB/s (single channel)
Dual channel: ×2 = 76.8 GB/s
This is why DDR5-4800 dual-channel bandwidth is 76.8 GB/sPrefetch Depth: The Secret to Why DDR Frequency Doesn’t Increase But Bandwidth Does
When DDR accesses memory, it “prefetches” a block of data into the I/O buffer. The size of this block is called the Prefetch Depth.
DDR1 / DDR2 / DDR3 / DDR4 / DDR5 prefetch depth:
DDR1: 2n prefetch
→ Core reads 2 bits per access
→ I/O transmits 2 bits per clock cycle (one on each edge)
→ Core frequency = I/O frequency
DDR2: 4n prefetch
→ Core reads 4 bits per access
→ I/O transmits 2 bits per cycle
→ Core frequency = I/O frequency / 2
DDR3: 8n prefetch
→ Core reads 8 bits per access
→ Core frequency = I/O frequency / 4
DDR4: 8n prefetch (same as DDR3)
→ Still 8 bits per access
→ Core frequency = I/O frequency / 4
→ Higher bandwidth by increasing I/O clock
DDR5: 16n prefetch
→ Core reads 16 bits per access
→ Core frequency = I/O frequency / 8
→ BC16 burst mode supports even larger data fetching
The prefetch mechanism allows the core to run at a lower frequency
while the I/O interface runs at a much higher frequency:
DDR5-6400: Core @ 800MHz, I/O @ 3200MHz → 4× ratioDiagram showing prefetch:
Memory Core (800MHz):
[R][R][R][R][R][R][R][R][R][R][R][R][R][R][R][R]
| | | | | | | | | | | | | | | | |
16n prefetch buffer
| | | | | | | | | | | | | | | | |
I/O Mux (parallel → serial)
| | | | | | | | | | | | | | | | |
I/O pins (3200MHz DDR): each pin transfers 2 bits per core cycle
──R0──R1──R2──R3──R4──R5──R6──R7──R8──R9──R10──R11──R12──R13──R14──R15──
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