Typical memory datasheet structure:

1. Overview
   - Capacity, model number, voltage, package

2. Architecture
   - Organization (e.g., 1G × 8, 2G × 4, etc.)
   - Number of banks, rows/columns count

3. DC Characteristics
   - Voltage range, power consumption, I/O standard

4. AC Characteristics
   - Timing parameters (tCL, tRCD, tRP, tRAS, etc.)

5. Pin Description
   - Function of each pin

6. Command Truth Table
   - Encoding of ACT, READ, WRITE, PRE, REF commands

7. Package Dimensions
   - Size, pin pitch

Capacity notation: Organization × bit width

Example: MT40A512M16HX-062E:B

Breakdown:
  MT40A = Micron 40A series (40nm process)
  512M = 512 Megabit (not Byte!)
  16 = ×16 bit width
  HX = DDR4-2666 (HX = DDR4-2666 model code)
  062E = 62E package (FBGA, 78-ball)
  :B = Revision

Total capacity = 512 Mb = 64 MB (8 bits/byte)

If a DIMM is built with 16 such chips for 8GB:
  16 chips × 64 MB = 1024 MB = 1 GB ... wrong?
  512 Mb = 0.5 Gbit = 0.0625 GByte
  16 chips × 0.5 Gbit = 8 Gbit = 1 GB

  16 chips × 16-bit = 256-bit total width
  256 / 8 = 32 bytes parallel... this is a dual-rank 16GB configuration

DDR4 speed grades (JEDEC standard):

DDR4-2133: 2133 MT/s, CL=15, tRCD=15, tRP=15
DDR4-2400: 2400 MT/s, CL=17, tRCD=17, tRP=17
DDR4-2666: 2666 MT/s, CL=19, tRCD=19, tRP=19
DDR4-3200: 3200 MT/s, CL=22, tRCD=22, tRP=22

MT/s meaning:
  DDR4-3200 = 3200 Mega Transfers per second = 3.2 GT/s

Actual clock frequency:
  3200 / 2 = 1600 MHz (DDR is double-edged)

CL (CAS Latency):
  Time from issuing Column address to data appearing at output
  DDR4-3200 CL22 ≈ 13.75ns (22 / 3200 × 1000)

  Smaller number = lower latency.

DDR4 main timing parameters:

tCL (CL, CAS Latency):
  Number of clock cycles from READ command to valid data output
  CL=15 → 15 clock cycles before data is available

tRCD (RAS to CAS Delay):
  Time between ACT (activate row) and READ/WRITE (column access)
  tRCD=13.5ns (DDR4-2400)
  Too long increases access latency

tRP (Row Precharge Delay):
  Time between PRE (precharge) and ACT (re-activate)
  tRP=13.5ns (DDR4-2400)

tRAS (Row Active Time):
  Minimum time a row must stay open after ACT
  tRAS = 35ns (varies by spec)

tRFC (Refresh Cycle Time):
  Time needed to complete a refresh operation
  tRFC = 350ns (DDR4-8Gb)
  The longest single timing parameter

tCCD (Column to Column Delay):
  Minimum interval between two consecutive READ/WRITE commands
  tCCD = 4 cycles (DDR4)
  Determines memory bandwidth ceiling

Using timing parameters to calculate latency:

DDR4-3200 CL22:
  tCL = 22 cycles × (1/1600 MHz) = 13.75ns
  tRCD = 22 cycles × (1/1600 MHz) = 13.75ns
  tRP = 22 cycles × (1/1600 MHz) = 13.75ns

Random read latency (page miss):
  tRP (close old row) + tRCD (activate new row) + tCL (read data)
  = 13.75 + 13.75 + 13.75 = 41.25ns

Sequential read latency (page hit):
  tCL = 13.75ns

Conclusion: Page miss is 3× slower than page hit

Example 1: Micron MT40A512M16HX-062E:B

  Look at the datasheet:
  1. Overview section: DDR4 SDRAM, 512Mb × 16 = 8Gb total
  2. Speed: DDR4-2666, CL19-19-19
  3. Voltage: VDD=1.2V, VPP=2.5V
  4. Architecture: 8 Banks, 16 KB page size
  5. Package: 78-ball FBGA

Example 2: Comparing two memory sticks for latency:

  DDR4-3200 CL22: first-word latency = 22 / 1600 MHz = 13.75ns
  DDR4-2666 CL19: first-word latency = 19 / 1333 MHz = 14.25ns

  DDR4-3200 CL22 actually has lower latency than DDR4-2666 CL19!

  Important: Always calculate actual time (ns), not just CL value
  because clock frequency affects the final latency