Bit Flip:

  Physical causes:
    - Cosmic rays (high-energy particles) hitting a DRAM cell
    - Alpha particles emitted from packaging materials
    - Electromagnetic interference (EMI)
    - Temperature-induced charge leakage

  Occurrence frequency:
    - Without ECC memory: approximately 100~1000 bit flips per GB per month
    - Large data centers: thousands of errors may occur daily
    - Modern servers must address this or data integrity cannot be guaranteed

Error types:
  - Single Bit Error: Only 1 bit flips
  - Multi-Bit Error: 2 or more bits flip simultaneously
  - Row/Column Failure: An entire row or column of cells fails

Parity principle:

Data: 8-bit data to transmit (e.g., 10110011)

Add a parity bit so that the total number of "1"s is even (even parity) or odd (odd parity):

  10110011 (8 bits)
  + parity bit = 1 (total 6 ones, already even, parity = 1)

  Transmit: 101100111 (9 bits)

Receiver: Count the number of "1"s
  - If even, data is considered correct (even parity)
  - If odd, an error is detected

Limitations:
  - Can only detect an odd number of bit flips (1 flip detected, 2 flips undetectable)
  - Cannot correct errors (doesn't know which bit is wrong)
  - Additional 1/9 overhead (12.5%)

ECC = Parity that can correct errors

Core idea of Hamming Code:

Group the data, add several parity bits to each group,
where each parity bit's value is computed from a specific subset of data bits.

Receiver: Check which parity bits are wrong to locate the specific erroneous bit.

Hamming Code calculation (using 8-bit data as example):

Original data: D7 D6 D5 D4 D3 D2 D1 D0 (8 bits)

Hamming Code layout (12-bit):
  P1 P2 D7 P3 D6 D5 D4 P4 D3 D2 D1 D0

  P1: Checks D7,D6,D4,D3,D1 (positions following a pattern: 1,2,4,8,16, etc.)
  P2: Checks D7,D5,D4,D2,D1
  P3: Checks D6,D5,D4,D0
  P4: Checks D3,D2,D1,D0

  XOR of P1/D7/D6/D4/D3/D1 = value of P1
  XOR of P2/D7/D5/D4/D2/D1 = value of P2
  ...

  Verification: Calculate XOR of all parity bits that include the target bit
  If the result is 1, that bit is erroneous
  Multiple parity bits simultaneously wrong = locate the specific bit

Server ECC memory module (64-bit data channel):

Data bits: 64 bit (without ECC, directly transmits 64 bits)
ECC bits: 8 bit (every 64 bits of data + 8 bits of error correction code)

Total width: 72 pins (64 + 8 = 72 bits)

How it works:
  CPU → Memory controller
    → Memory controller calculates ECC code (8 bits) for 64-bit data
    → Transmit: 64-bit data + 8-bit ECC

  On read:
    → Memory controller receives 64-bit data + 8-bit ECC
    → Recalculates ECC and compares with received ECC
    → If different, locates and corrects single-bit error
    → If ECC discrepancy is too large (2+ bit errors), reports unrecoverable error (SRAO/UCNA)

ECC vs. Non-ECC comparison:

                       Non-ECC              ECC (SECDED)
Data bits per access      64                     64
Check bits                 0                      8
Total pins                 64                     72
Error detection            None              All 1-bit + some 2-bit
Error correction           None                   1-bit
Latency overhead          0                    ~1-2 cycles
Module cost            Baseline                 +10-20%
Application           Desktops/gaming        Servers/workstations

SECDED = Single Error Correction, Double Error Detection

Limitations of standard ECC:

Standard ECC (SECDED):
  - Corrects 1 bit error per 64-bit word
  - Detects 2 bit errors per 64-bit word
  - If an entire DRAM chip fails (e.g., a x4 or x8 chip), ECC cannot recover

Advanced protection:

Chipkill (IBM, Intel):
  - Distributes data and ECC across multiple chips
  - Can tolerate one complete chip failure
  - Overhead: more ECC bits, more complex controller

SDDC (Single Device Data Correction, Intel):
  - Similar to Chipkill concept
  - Corrects errors from a single DRAM device failure
  - Standard on Xeon platforms

Rank Sparing / Memory Mirroring:
  - Entire rank as backup
  - On failure, transparently switch to backup rank
  - 50% capacity overhead