358 | Timer: HPET and Clock Interrupts Key Insight: The operating system’s sense of time doesn’t come from “watching a clock” — it’s “punched out” by interrupts. Each clock tick tells the kernel that another jiffy has passed — and then it decides who gets to run next. 1. Three Clock Hardware Components The x86... » read more

S01 — DRAM: How One Capacitor and One Transistor Store One Bit Key Insight: Behind complex systems, there are often just a few simple physical principles at work. Understanding DRAM starts with the most fundamental Cell. 1. Physical Structure of a DRAM Cell 1.1 What Is DRAM DRAM (Dynamic Random Access Memory) is the main... » read more

B09 — What Happens When Memory Runs Low: kswapd and Page Frame Reclaim Key Insight: When memory runs tight, the system quietly moves infrequently used data to disk. This is swapping. Sources of Memory Pressure Linux always starts tidying up when memory approaches full. It swaps out infrequently used pages to disk, making room for... » read more

333 – Android Zygote: The Incubator for All App Processes Series Navigation: 330-Boot Overview | 331-Bootloader | 332-init Process In the previous article, we covered the init process — the first userspace process, responsible for parsing configuration, mounting filesystems, managing properties, and starting key services. The most important of these services is Zygote. Zygote is... » read more

K08 — Inter-Process Shared Memory: shm and mmap(MAP_SHARED) Key Insight: The fastest inter-process communication is no communication at all — directly share the same block of memory. Three Ways to Share Memory Between Processes Linux supports three mechanisms for inter-process shared memory: 1. System V Shared Memory (shmget/shmat) - Long history, pre-POSIX API - Managed... » read more

Writing an OS Kernel from Scratch | GPT Partition: How to Break MBR’s 2TB Limit and Manage 128 Partitions In the previous article we covered MBR — the 512-byte first sector, 446 bytes of bootloader plus 64 bytes of partition table. MBR dominated PC partitioning standards for 30 years, but it has two unavoidable hard... » read more

B06 — The Manager of Physical Memory: The Buddy System Key Insight: Grouping memory into “buddies” makes both allocation and reclamation efficient. Why Do We Need the Buddy System The OS needs to manage physical memory allocation and reclamation. The simplest approach is bitmap management, but it is inefficient for allocating large blocks. 位图管理的问题： 假设用... » read more

Writing an OS Kernel from Scratch | Display — From Framebuffer to GPU Have you ever wondered: How is a single pixel lit up on the screen? The CPU only sends a few bytes of data, yet the display can render a complete Windows desktop or game scene. The chain in between — Framebuffer, DRM/KMS,... » read more

K01 — Object Management After Physical Page Allocation: The SLAB/SLUB Allocator Key Insight: Placing fixed-size objects on fixed-size pages is the core of memory allocator design. Why SLAB Is Needed After the Buddy System The Buddy System manages 4 KB, 8 KB, 16 KB… 4 MB physical page frames. But the kernel needs to allocate... » read more

A11 — The Memory Boundary Between User and Kernel: Zero-Copy Technology Key Insight: The fastest path from disk to network is to not copy at all. Memory Boundary Between User Mode and Kernel Mode User programs and the kernel have separate address spaces. Interaction requires system calls or specific mechanisms. 用户态和内核态的隔离： 用户地址空间（0x00000000 ~ 0x7FFFFFFFFFFF）： -... » read more

S02 — Why Does DRAM Need “Refresh”? The Essential Difference Between SRAM and DRAM Key Insight: SRAM latches data with transistors, DRAM stores data with capacitors — one remembers forever as long as power is on, the other must periodically “recharge” to retain data. 1. The Essence of the DRAM Refresh Problem 1.1 Physics of... » read more

B05 — How the MMU Translates Virtual Addresses to Physical Addresses Key Insight: Behind every virtual address is a complex translation process. And you never perceive it. What is an MMU The MMU is a hardware unit on the CPU chip. It translates Virtual Addresses (VA) to Physical Addresses (PA). MMU 在系统中的位置： CPU Core Memory... » read more

Understanding Low-Level Principles – Memory Series | S05 | Bank, Row, Column — How a Memory Address is Step-by-Step Mapped to a Specific Cell Key Insight: Translating an address into a physical access requires many layers of abstraction. Understanding Bank internal structure is the key to understanding DDR performance. 1. DRAM Chip Internal Structure: The... » read more

Writing an OS Kernel from Scratch | 351: NIC — From PHY to Socket Abstract: The network card is the gateway for a computer to connect to the network. Data travels from the application socket all the way through the protocol stack, driver, bus, and reaches the PHY, finally becoming optical/electrical signals transmitted over the... » read more

# Writing an OS Kernel from Scratch – Part 35: TCP/IP Protocol Stack — Using socket to GET the Baidu Homepage! “The NIC driver is just the hardware interface; real networking capability lies in the protocol stack. Today, we implement a minimal TCP/IP stack and use a user-mode program to download the Baidu homepage!” In... » read more

# Writing an OS Kernel from Scratch – Part 13: sysfs — Exposing Kernel Information as Files “Kernel runtime state is hidden in registers and memory — how can users view it? Today, we implement sysfs, making CPU, memory, and process information readable like regular files!” In the previous article, we got standard streams (stdin/stdout/stderr)... » read more

Writing an OS Kernel from Scratch | Windows Boot Manager vs GRUB: A Complete Analysis of Two Boot Loaders From 360 to 362, we covered the BIOS/UEFI → MBR/GPT → GRUB boot chain. GRUB is the standard bootloader for Linux, but Windows uses a completely different system — BOOTMGR (Boot Manager) and BCD (Boot Configuration... » read more

Writing an OS Kernel from Scratch | 348: I2C Bus — The Blood Vessels of Embedded Systems Abstract: I2C is the most common low-speed bus in embedded systems. With just two wires, it can connect a large number of devices — sensors, EEPROMs, RTCs, touchscreen controllers… This article covers I2C protocol principles, master-slave architecture, and... » read more

A03 — Multi-threaded malloc: Arena Contention and Per-thread Arena Key Insight: In multi-threaded scenarios, every malloc is a potential contention point. ptmalloc uses arenas to solve this problem. The Problem with Multi-threaded malloc In single-threaded programs, malloc contention is rare (only one heap). But in multi-threaded programs, all threads share the same heap. Without special... » read more

Writing an OS Kernel from Scratch | Synchronization Primitives — spinlock and semaphore, How the OS Coordinates Concurrent Access Two processes write data to the same file simultaneously — process A writes the first 100 bytes, process B writes the next 100 bytes. If no coordination is done, what happens? Process A just read the... » read more