354 | Interrupt Controller: How Hardware Interrupts the CPU

Key Insight: You press a key, and a character appears on the screen almost simultaneously — behind this, the CPU has never been “waiting” for the keyboard. It has been running its own code the whole time, until the hardware forcibly “interrupts” it.

1. Problem: How Does the Keyboard Get Characters to the Screen?

You type an a in the terminal, and the character instantly appears on the screen. This process seems simple, but behind it lies a set of hardware coordination mechanisms:

Keyboard Hardware → IRQ1 Interrupt → 8259A PIC → CPU Pin → Interrupt Handler → Terminal Driver → Screen

The key issue is: Before being interrupted, the CPU has no idea what the keyboard is doing. It can’t stop and poll each device — that would be far too inefficient.

The solution is Interrupts: The CPU just runs its own code. When a device has something to report, it “knocks on the door proactively” — it initiates an interrupt to the CPU via a hardware signal line, forcing the CPU to stop its current work and execute a dedicated interrupt handler.

This article dissects the chain: 8259A PIC, IOAPIC, LAPIC, MSI — how these hardware components step by step deliver peripheral interrupts to the CPU.

2. What Is an Interrupt Controller?

The CPU has only a few dedicated pins for receiving interrupts (e.g., x86’s INTR and NMI). But a computer has dozens of devices (keyboard, mouse, hard disk, network card…), each capable of sending interrupts.

An Interrupt Controller is the “operator” connecting all peripherals and the CPU: it receives interrupt requests (IRQs) from various devices, sorts them by priority, converts them into vector numbers the CPU can understand, and notifies the CPU via the INTR pin.

  Keyboard ──IRQ1──┐
  Mouse ──IRQ12────┤      ┌────────────┐      ┌──────┐
  HDD ──IRQ14──────┼──→  │ 8259A PIC  │ ───→ │ CPU  │
  NIC ──IRQ5───────┘      └────────────┘      └──────┘
                        (Master + Slave Cascade)

Without an interrupt controller, the CPU would need a dedicated interrupt line for each device — impossible on a PC with dozens of devices.

3. 8259A PIC: The Classic Programmable Interrupt Controller

3.1 Historical Background

Intel introduced the 8259A PIC (Programmable Interrupt Controller) in 1976. It has 8 interrupt input pins (IRQ0-IRQ7), expandable to 15 via cascading. The IBM PC/AT standard configuration was two-level cascading: a master chip (IRQ0-IRQ7) and a slave chip (IRQ9-IRQ12 share IRQ2).

         CPU
          ↓ INTR
      ┌─────────┐
      │ 8259A   │  Master (Main Controller)
      │ (Master)│
      └────┬────┘
           │ IRQ2 (Cascade)
      ┌────┴────┐
      │ 8259A   │  Slave (Secondary Controller)
      │ (Slave) │
      └─────────┘

3.2 Internal Structure

The 8259A has several key internal registers:

• IRR (Interrupt Request Register): Records which IRQs are waiting to be processed
• ISR (In-Service Register): Records which IRQs are currently being processed by the CPU
• IMR (Interrupt Mask Register): Software can mask certain IRQs

The priority arbitration logic picks the highest priority request from the IRR each time and sends it to the CPU.

3.3 Interrupt Vector Numbers

The 8259A supports two modes:

• Non-buffered mode: Places the vector number on the data bus itself
• x86 real mode: Starting vector base is 0x08 (master) and 0x70 (slave)

Default x86 PC mapping: