Memory bandwidth = Prefetch width × Clock frequency × Data rate multiplier / Transfer unit

DDR5 improvements come from three dimensions:
  1. Clock frequency increase: DDR4 max 3200MHz → DDR5 max 6400MHz
  2. Prefetch width doubled: DDR4 BC8 (8 Burst) → DDR5 BC16 (16 Burst)
  3. Channel subdivision: DDR5 implements dual channels within a single DIMM (40bit vs 64bit)

DDR4-3200 (dual channel, 64bit bus):
  3200 MT/s × 64 bit / 8 = 25.6 GB/s

DDR5-4800 (dual channel, 40bit × 2 subdivision):
  4800 MT/s × 40 bit × 2 / 8 = 48 GB/s (87% improvement)

DDR5-6400:
  6400 MT/s × 40 bit × 2 / 8 = 64 GB/s (150% improvement)

DDR4 (no Bank Groups):
  16 Banks = 4 Groups × 4 Banks
  Only one Bank can be operated at a time (limited cross-bank parallelism)

DDR5 (2 Bank Groups):
  32 Banks = 2 Groups × 4 Banks × 4 Banks
  Two Bank Groups can perform different operations simultaneously:

  Group 0: Currently in READ (transferring data)
  Group 1: Simultaneously in ACT (row activation)

  The tRP latency of row conflicts can be hidden by operations in the other group

Burst Length = amount of data fetched per column access

DDR4 BC8 (8 Burst):
  One column access fetches 8 × 8 bytes = 64 bytes (one Cache Line)
  Suitable for 64B Cache Line systems

DDR5 BC16 (16 Burst):
  One column access fetches 16 × 8 bytes = 128 bytes
  Suitable for larger Cache Lines (future 128B trend)

Advantage:
  At the same tCCD, BC16 fetches twice as much data per access as BC8
  Higher bandwidth utilization, especially in large data block transfers (video encoding/decoding, AI inference)

DDR4 DIMM (64bit):
  One DIMM = 64 bit data bus
  Two DIMMs in dual channel = 64 × 2 = 128 bit

DDR5 DIMM (40bit × 2):
  One DIMM has 2 internal 40-bit sub-channels (like two small DIMMs)
  40 bit = 32 bit data + 8 bit ECC (if applicable)

  The same DDR5 DIMM can access both sub-channels in parallel
  Equivalent to having "dual channel" already inside one DIMM

Benefits:
  - Memory controller only needs to support 40bit, not 64bit
  - Motherboard routing is simpler (fewer DQ pins)
  - Lower power consumption (each channel has lighter load)

NRZ (Non-Return-to-Zero) encoding:
  → Signal level has only two states: high (1) and low (0)
  → Each symbol encodes 1 bit
  → Signal level stays constant during a clock cycle (does not return to zero)

NRZ signal diagram:

  1     0     1     1     0     0     1     0
  ─┐   ─┐   ──┐ ──┐   ─┐   ─┐   ──┐   ─┐
    └───┘ ──┘    └───┘ ──┘ ──┘    └───┘

Limitations of NRZ:
  - At higher frequencies, signal integrity degrades
  - Inter-symbol interference (ISI) worsens
  - DDR5 uses PAM-3 to break through this bottleneck

PAM-3 (3-level Pulse Amplitude Modulation):
  → Signal level has three voltage states: -1, 0, +1
  → Each symbol encodes log2(3) ≈ 1.58 bits
  → Compared to NRZ's 1 bit/symbol, 58% more data per symbol

PAM-3 signal diagram:

  +1 ──┐   ┌──┐   ┌──┐   ┌──    ┌───┐
   0    └───┘  └───┘  └───┘  ──┘│   └───
  -1                              └───────

PAM-3 encoding in DDR5:
  → Used for command/address signals (CA bus)
  → NRZ still used for DQ data (to maintain backward compatibility)
  → Reduces the number of CA pins, saving package cost

Comparison:
  ┌────────┬──────────┬────────────┬──────────────────┐
  │ Encoding│ Bits/sym │ SNR req.   │ Application       │
  ├────────┼──────────┼────────────┼──────────────────┤
  │ NRZ    │ 1.0      │ Low        │ DDR4, DDR5 DQ     │
  │ PAM-3  │ 1.58     │ Medium     │ DDR5 CA bus       │
  │ PAM-4  │ 2.0      │ High       │ GDDR6X, future    │
  └────────┴──────────┴────────────┴──────────────────┘