Slight Improvements to the 80486

The 80286 added segmented memory management and protected mode. The 80386 added paged memory management. These both had an enormous influence on modern operating systems. Because after the improvements in the 386, no more changes of such magnitude took place — the 80386 became a timeless classic. So much so that until 64-bit CPUs appeared, every CPU after the 386 was essentially used as a 386.

Packaging

Students who have worked with microcontrollers may feel that the packaging of the 80486 is similar to the popular microcontrollers of today; in fact their performance is also roughly comparable.

The 80486 came in several different models, and the packaging of each model was not quite the same. For details, you can refer to the many photos here:
http://www.mynikko.com/CPU/80486.html

Process: 1 µm, 800 nm, 600 nm

Internal Structure

Model Differences

Cited from: https://zh.wikipedia.org/wiki/Intel_80486
Intel 80486SX – i486 without FPU support. Because the FPU in early i486s had defects, the FPU function was disabled; in later versions, to reduce cost and die area, the FPU was removed entirely.
Intel 80486DX – i486 with FPU.
Intel 80486DX2 – processor that runs at 2x clock multiplier.
Intel 80486SX2 – same as i486DX2, but without the FPU function.
Intel 80486SL – low-power i486DX, primarily used in portable computers.
Intel 80486SL-NM – low-power i486SX.
Intel 80487 – math coprocessor for use with the i486SX; in fact the 80487 is a complete i486DX processor. When the 487 is installed, it disables the i486SX and takes over all processor work.
Intel 80486 OverDrive – processor with a faster internal operating speed.
Intel 80486DX4 – processor that runs at 3x clock multiplier (not 4x).
The i486 clock speeds included 16, 20, 25, 33, 40, 50, 66, 75, 100 MHz.

Added Instructions

Compared to the 386, the 80486 only added a few instructions. They are:

XADD: an atomic arithmetic instruction, i.e. fetch and add

BSWAP: byte-order swap instruction, which reverses the byte order of a 32-bit value, turning the original bytes 0, 1, 2, 3 into 3, 2, 1, 0. Reference: https://c9x.me/x86/html/file_module_x86_id_21.html

CMPXCHG: compare and swap atomic instruction, http://x86.renejeschke.de/html/file_module_x86_id_41.html

INVD: invalidates the internal cache; the 80486 has a Level 1 cache integrated inside the CPU. This instruction is used to flush the cache contents.

WBINVD: write back and invalidate data. Invalidates the internal cache, and before invalidation writes any modified data back to memory.

INVLPG: invalidates a TLB entry. The difference between this instruction and directly loading CR3 is that CR3 invalidates the entire TLB and reloads it. INVLPG, on the other hand, invalidates the TLB entry for a specific page. It is a finer-grained control. For the difference between it and CR3, see this discussion: https://stackoverflow.com/questions/28384234/when-to-do-or-not-do-invlpg-mov-to-cr3-to-minimize-tlb-flushing

Frequency

The 80486 still used very slow clock frequencies, with a minimum of 20 MHz and a maximum of 100 MHz. But the 80486 implemented clock multiplication, using a special circuit that caused most internal components to run at 2x or 3x the input clock speed (at the time 3x was the highest supported).

Modern desktop CPUs typically have clock frequencies of 200 MHz, but the CPU’s main frequency is generally around 3 GHz — also using clock multiplication technology.

Level 1 Cache and Integrated Floating-Point Coprocessor

The 80386 had intended to integrate an L1 cache, but for various reasons never managed to. The 80486 finally achieved this. It has a built-in 8 KB L1 cache, and does not distinguish between data and instructions — both are cached on this single cache.

The floating-point coprocessor, previously sold separately as an x87 device, was finally integrated into the 80486. However, there was a problem: some production batches had faulty floating-point coprocessors, so Intel disabled the floating-point coprocessor on those batches of CPUs and sold them as versions without built-in x87 support. Some users genuinely did not need a coprocessor and would buy them; if they later discovered they needed a coprocessor, they would buy an x87 and install it externally.

   The performance of the 80486 was 4 times that of the 80386 with an 80387. Early 486s were split into two types: the 486DX with a coprocessor and the 486SX without one, and their prices differed substantially.

Cited from Baidu Baike

Multi-pipeline (pipelining)

Multi-pipeline is a technique that was first used in RISC CPU architectures, so when the 80486 adopted multi-pipeline, some people said it supported RISC.
In the 80386, executing one instruction required two clock cycles. After adopting multi-pipeline, in the 80486 some instructions needed only one clock cycle. These were mainly register-to-register and register-to-cache instructions in the ALU.

Multi-pipeline means that the CPU has a pipeline during instruction fetch. The four units of the 80486 (bus unit, decode unit, execute unit, write-back unit) can each be pipelined and operate simultaneously — at the same time one instruction is being executed, the previous instruction is being written back, the next instruction is being decoded, and the one after that is being fetched by the bus. Specifically, it works like this: