The 80386 Cache

Everyone knows that cache is used to address the speed mismatch between the CPU and memory. The 80386 was the first CPU in x86 computers to be equipped with cache.

The GAP Between CPU and Memory Speeds

First, let us see whether this gap exists, and when it began to appear.

Below, we list the clock frequencies of the 8086, 80286, and 80386, along with the performance of the memory they used. The following two tables were found online and show the clock frequencies of CPUs from different eras and DRAM memory access times, respectively. Source:http://www.qdpma.com/CBO/InMemory.html

Year	DRAM	Density	tRAC
1971	Intel 1103	1K	300ns
1973	TI TMS403	4K	?
1977	Mostek MK4116	16K	250ns
1980	?	64K	200ns
1983	?	256K	150ns
1986	?	1M	?
1989	?	4M	80ns
1992	?	16M	?
1995	?	64M	?

DRAM Access Time Table

	MHz	MIPS	transistors	process	Year
Intel 4004	0.740	0.07	2,300	10µm	1971
Intel 8080	2	0.29	6,000	6µm	1974
Intel 8086	5 8	0.33 0.66	29,000	3µm	1978
Intel 80286	6 12.5	0.9 2.66	134,000	1.5µm	1982
Intel 80386DX	16 33	5 9.9	275,000	1µm	1985 1989
Intel 80486DX	25 50	20 41	1.2M	1µm 0.8µm	1989 1991
Intel 80486DX4	75 100	53 70.7	1.6M	0.6µm	1994
Intel Pentium (P5)	60 66	100 112	3.1M	0.8µm	1993
Intel Pentium (P54)	90 100	149.8 166.3	3.2M	0.6µm	1994
Intel Pentium (P54CS)	133 166	218.9 247	3.3M	0.35µm	1995 1996

Table of Changes in CPU Clock Frequency

The tables show that when the 80386 was released, memory access time was at least greater than 80ns. If we make a rough estimate and use 100ns, memory could be accessed no more than 10 million times per second, while the 80386’s clock frequency reached as high as 33MHz. If instructions were fetched in real time, memory could no longer meet the CPU’s demands at that time.

The 80386 Cache

Because memory access speed had begun to lag behind CPU speed at that time, users had three choices: pay a high price for the fastest memory, add an external cache, or simply use slower memory and prevent the CPU from reaching its maximum performance. The 80386 was originally intended to place L1 cache inside the CPU, but this was ultimately not achieved, so it instead supported an external cache. The 80486 succeeded in placing L1 cache (8KB) inside the CPU while also supporting an external L2 cache.

It was not until the Pentium era that, because the Pentium used a dual-issue superscalar architecture with two parallel integer pipelines, it needed to access data and instructions simultaneously. To prevent these accesses from interfering with each other, an 8K data cache and an 8K instruction cache appeared—that is, L1 was divided into an instruction cache and a data cache—and both could be read and written simultaneously. L2 was still external, however. The Pentium Pro that followed embedded L2 to improve performance. At this point, the basic model of modern cache was established, and it has remained in use to this day.

For cache to work, it relies on the locality of data when the CPU accesses it. That is, if the address you are accessing now is A1, there is a high probability that you will next access data before or after A1. Therefore, when the CPU detects that you have accessed the data at A1, it can fetch nearby data into cache in advance. Because cache access is very fast, if the data you access next is indeed already in cache, that memory access becomes extremely fast.