Writing an OS Kernel from Scratch | 351: NIC — From PHY to Socket

Abstract: The network card is the gateway for a computer to connect to the network. Data travels from the application socket all the way through the protocol stack, driver, bus, and reaches the PHY, finally becoming optical/electrical signals transmitted over the network cable. This article starts with the MII/PHY physical layer and explains in detail the netdev driver framework, ethtool debugging, and ring buffer working principles. wandos currently has no network stack implementation.

1. Network Layering and NIC Position

1.1 Layering of the Network Protocol Stack and NIC

User Space (Applications)
    ↓ send()/recv() socket API
Kernel Protocol Stack (TCP/IP/UDP/ARP)
    ↓ sk_buff (socket buffer)
NIC Driver (igb, e1000, r8169, virtio-net...)
    ↓ DMA Descriptor
PCIe Bus (Ethernet frame)
    ↓
NIC + PHY
    ↓
Network Cable / Optical Fiber

The network card sits below the protocol stack. The driver is responsible for sending sk_buff (the kernel’s network buffer) via DMA to the NIC’s TX queue, which is then transmitted by the NIC hardware over the network cable. In the reverse direction, the NIC receives frames, triggers DMA to the RX queue, generates a hard IRQ, the driver reads the data, constructs sk_buffs, and sends them up the protocol stack.

1.2 PHY vs MAC: Who Does What

┌─────────────────────────────────────────────────────┐
│                    Motherboard / SoC                  │
│  ┌─────────┐        ┌──────────────┐                │
│  │   CPU   │◄──►    │  MAC Ctrl    │                │
│  │         │  AXI/  │  (Media      │                │
│  │         │  PCIe  │  Access Ctrl)│                │
│  └─────────┘        └───────┬───────┘                │
│                             │ MII/RGMII/RMII        │
│                      ┌──────▼───────┐                │
│                      │     PHY      │                │
│                      │ (Physical    │                │
│                      │  Layer Chip) │                │
│                      └──────┬───────┘                │
│                             │ RJ45 / Optical Fiber    │
└─────────────────────────────┴─────────────────────────┘

• MAC (Media Access Controller): Responsible for Ethernet frame assembly/parsing, CRC calculation, DMA control, located inside the SoC/southbridge
• PHY (Physical Layer): Responsible for encoding (Manchester/64b66b), clock recovery, signal driving, an independent chip

1.3 MII Family: Connecting MAC and PHY

RGMII is currently the most commonly used MAC-PHY interface, using a DDR clock (sampling on both rising and falling edges), achieving Gigabit speeds with only 4 data lines.

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