Writing an OS Kernel from Scratch – Part 18: Multi-core Support — Make Your OS Truly Parallel!
“Single-core scheduling is just pseudo-concurrency; the real performance leap is multi-core! Today, we wake up all CPU cores and implement SMP (Symmetric Multi-Processing) support!”
In the previous post, we implemented a preemptive scheduler, but all tasks still switched on a single CPU core. Modern processors are universally multi-core (dual-core, quad-core, or more). A real OS must utilize all cores to achieve true parallel computing.
x86 Multi-core Boot Basics: BSP and AP
In an x86 multi-processor system at boot:
- BSP (Bootstrap Processor): the first booting core (usually Core 0)
- AP (Application Processor): other cores, initially in sleep state
Standard AP startup protocol: MP Specification or ACPI MADT
Key steps:
- BSP parses the MP table, getting CPU core count and LAPIC IDs
- BSP sends INIT/SIPI messages via LAPIC to wake APs
- AP starts executing from a specified address (usually 0x10000)
LAPIC (Local APIC) is each core’s interrupt controller and key to inter-core communication.
Kernel Synchronization: Spinlocks and Atomic Operations
Multi-core concurrent access to shared data must be synchronized:
- Atomic operations (inline assembly)
- Spinlocks
Spinlocks must disable interrupts while held (to avoid deadlock)!
Multi-core Scheduler Transformation
- Each core has an independent run queue
- Get current core ID
- Scheduler functions modified for per-core operation
- Load balancing (optional): periodically check other cores’ run queues, migrate tasks if unbalanced
Inter-Processor Interrupts (IPI)
LAPIC supports IPI for:
- Scheduling requests: one core wakes another
- TLB flush: one core modifies page table, notifies other cores
- Shutdown/restart
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