B02 — The ID Card of RAM: What’s Actually Stored in the SPD Chip
Key insight: RAM without SPD is like a person without ID — the system doesn’t know who it is.
SPD Chip Basics
Every DDR memory module has an SPD (Serial Presence Detect) chip, a 256-byte (or 512-byte for DDR5) EEPROM.
SPD Chip Specs:
Capacity: 256 Bytes (DDR4), 512 Bytes (DDR5)
Package: 8-pin SOIC, 3mm × 5mm
Location: Near the right side of the memory module's edge connector (next to the notch)
Communication: I2C bus, address 0x50/0x51/0x52 (Channel 0/1/ECC)
I2C Bus Characteristics:
- Clock frequency: 400kHz (Fast Mode)
- Data format: MSB first
- ACK required after each byteSPD Byte Layout (DDR4 256 Bytes Detailed)
DDR4 SPD Structure (256 Bytes):
Byte 0~1: Manufacturer ID (0x80=Samsung, 0xAD=SK Hynix, 0x98=Micron, 0x9E=Crucial)
Byte 2: Manufacturer-specific (model encoding)
Byte 3: Die density (x4/x8/x16, 0x0C=8Gb)
Byte 4: Die organization (0x0A=8Gb x8 = 1GB per die)
Byte 5~6: Density (0x10=8GB, 0x20=16GB, 0x40=32GB)
Byte 7: Ranks (1=single rank, 2=dual rank, 4=quad rank)
Byte 8: Module banks (1=single-sided, 2=double-sided)
Byte 9: Voltage (0x06=1.2V, D9=1.35V DDR4L)
Byte 12~13: JEDEC standard frequency (0x0C=1600, 0x14=2133, 0x18=2666, 0x1E=3200)
Byte 16~17: JEDEC CL-tRCD-tRP-tRAS
Byte 20~21: XMP frequency (if XMP is present)
Byte 22~23: XMP timings (CL-tRCD-tRP-tRAS)
Byte 24~25: XMP voltage
Byte 30: Module type (0x02=DIMM, 0x01=SODIMM)
Byte 32~33: Module height (mm)
Byte 118~119: Serial number
Byte 122~123: Manufacturing Date (year/week)
Byte 127: Checksum (CRC/checksum of all preceding 127 bytes)
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