S08 — How Does an Address Travel from the CPU to a DRAM Cell
Key Insight: Every bit of data has its complete journey map.
The Complete Path from CPU to DRAM
How does an address issued by the CPU ultimately select a DRAM cell? It requires a complete address resolution process.
Complete path (simplified):
CPU (Virtual Address VA)
→ MMU translation (VA → PA) [detailed in K01]
→ Memory Controller
→ DDR protocol: Address decoding (Channel → Rank → Bank → Row → Column)
→ DRAM chip pins (row address + column address)
→ DRAM Cell access
Modern computer address resolution hierarchy:
VA (Virtual Address, 48-bit or 64-bit) → PA (Physical Address, 36~52 bit) → DRAM Address (Row/Col/Bank)Physical Address (PA) Width and Addressable Memory
The CPU's physical address width determines the maximum amount of memory the system can support.
Physical address width and memory limits:
36-bit physical address (traditional x86):
Max addressable = 2^36 = 64 GB
Typical: Intel Xeon early models, PAE mode
38-bit physical address (modern desktop x86):
Max addressable = 2^38 = 256 GB
Typical: Intel Skylake and later desktop CPUs
40-bit physical address (server-class x86):
Max addressable = 2^40 = 1 TB
Typical: AMD Zen architecture servers
48-bit physical address (ARM servers):
Max addressable = 2^48 = 256 TB
Typical: ARMv8-A server CPUs
52-bit physical address (theoretical max, ARMv8.2+):
Max addressable = 2^52 = 4 PB (not actually done, too expensive)Note: Physical address width ≠ the amount of memory you actually install. The system may only use part of the physical address space (e.g., only 32GB installed, but PA is 38-bit, supporting 256GB).
Memory Map: How Address Space Is Allocated
Physical address space is not entirely given to DRAM — part of it is reserved for MMIO (Memory-Mapped I/O) — i.e., device registers.
x86 physical address space allocation (typical 4GB address space system):
0x0000_0000 ~ 0x0009_FFFF: Traditional 640KB low memory area (IBM PC compatible)
0x000A_0000 ~ 0x000B_FFFF: Video RAM / VGA registers (128KB)
0x000C_0000 ~ 0x000F_FFFF: Hardware ROM area (BIOS/Option ROM, 640KB)
0x0010_0000 ~ 0xFFFF_FFFF: DRAM main area + MMIO
DRAM area: 0x0010_0000 ~ 0xDFFF_FFFF (approximately 3.5GB available, depends on system)
MMIO area: 0xE000_0000 and above (device registers)
ACPI tables, DMA buffers, device registers are in the MMIO area.
This is why a 32-bit system with 4GB of memory only has ~3GB available — the rest is occupied by MMIO.Address Bus Width and DIMM Slots
How many address lines the memory controller has determines how many DRAM chips it can address.
DDR4 address line configuration (64-bit dual channel):
Each channel has 51 address/command pins (some multiplexed):
- BA[2:0]: Bank Address (3 bit = 8 banks)
- BG[1:0]: Bank Group (DDR5 has this, 2 bit = 4 groups)
- RA[16:0]: Row Address (17 bit = up to 128K rows)
- CA[9:0]: Column Address (10 bit = up to 1K columns)
- CK/CK#: Clock
- CKE: Clock Enable
- CS#: Chip Select
- ODT: Impedance matching
Physical address to DRAM address mapping (simplified):
PA[35:30]: Reserved or Channel selection
PA[29]: Rank selection (dual-rank DIMM)
PA[28:18]: Row address (11 bits)
PA[17:12]: Bank selection (6 bits)
PA[11:6]: Column address (6 bits)
PA[5:0]: Byte offset within Cache LineComplete address translation example:
Virtual address: 0x7F00_1234_ABCD
→ Page table lookup (MMU):
Page directory → Page table → Physical page frame (PFN)
→ Physical address: 0x0000_3ABC_D000 + offset 0xBCD
Memory controller receives PA 0x0000_3ABC_DBCD:
→ Channel = PA[35:30] → Channel 0
→ Rank = PA[29] → Rank 0
→ Row = PA[28:18] → Row 0x3AB
→ Bank = PA[17:12] → Bank 0x3C (bank 60)
→ Column = PA[11:6] → Column 0xD
DRAM chip receives:
ACT command: Row address = 0x3AB, Bank = 60
→ Row decoder activates WL at row 0x3AB in bank 60
→ All 1024 cells in this row connect to Bit Lines
→ Sense amplifiers detect data
READ command: Column address = 0xD
→ Column decoder selects word at column 0xD from row buffer
→ 8 bytes (64 bits) output to DQ pins
→ After tCL delay, CPU receives the data
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