H05 — What Happens After RAM Powers On: SPD Chips and BIOS Memory Training

Key insight: Every RAM stick works normally in a computer because, in the instant of booting, someone does a lot of calibration work behind the scenes.

SPD Chip: The RAM’s “ID Card”

Every RAM module has an SPD (Serial Presence Detect) chip, an EEPROM storing the memory’s configuration info.

SPD chip location and specs:
- Location: Near right side of RAM module edge connector, usually next to the notch
- Package: 8-pin SOIC, 3mm × 5mm
- Capacity: 256 Bytes (DDR4) or 512 Bytes (DDR5)

SPD communicates with the memory controller via I2C bus:
  - Address: 0x50 (Channel 0), 0x51 (Channel 1), 0x52 (ECC)
  - Bus: I2C (SCL clock + SDA data)
  - Speed: 400kHz (I2C Fast Mode)

The motherboard reads SPD during POST (Power-On Self-Test):
  → BIOS knows what memory this is (capacity, speed, timings)
  → Automatically configures memory controller
  → Sets correct frequency, voltage, timings

BIOS POST Phase Memory Initialization

1. Reset and self-test → CPU reset, cache init → BIOS starts POST
2. Memory controller detection → scan how many channels, detect DIMM slots
3. Read SPD → I2C bus reads each DIMM’s SPD EEPROM
4. Select boot frequency → XMP/EXPO preferred, fall back to JEDEC
5. Memory Training → signal calibration for each DIMM, set timing parameters
6. Memory test → BIOS performs simple test (write/read verification)
7. Hand control to OS → write memory info to ACPI table