8th-Generation x86 Microarchitecture: Intel Core

The Core microarchitecture is a processor internal architecture designed from scratch, but it has a design similar to Pentium M. It has a 14-stage pipeline（Pipeline）, which is more than half shorter than the 31-stage Prescott of the NetBurst architecture. In addition, its execution core also increased from the 3 instructions per cycle of P6, P6-M, and Netburst to 4. This architecture is also a dual-core design, with the two cores’ L1 caches connected to each other and sharing L2 cache. The above design is used to achieve the highest performance per watt.

One new design is macro-fusion, which combines two x86 instructions into one for optimization. In addition, this architecture also shortens the latency of a 128-bit SSE instruction from two cycles to one cycle, along with a brand-new power-saving design. All cores run at the lowest speed and automatically increase speed when needed, reducing chip heat output and power consumption. The front-side bus (FSB) of this architecture is 1333 MHz (MT/s) for the Woodcrest core, 667 MHz (MT/s) for the Merom core, and 1066 MHz (MT/s, E6X00/Q6X00/QX6X00/X6X00) or 1333 MHz (MT/s, E6X50/E6X40/QX6X50) for the Conroe core. Unfortunately, the external frequency is also a weakness of this architecture, because it still uses the Pentium 4 core design, so it still cannot fully control dual-channel DDR2 memory, or the new FB-DIMM.

Intel claims its power consumption will be extremely low: the Conroe core will have a power consumption of 65 W, while the Woodcrest core is 80 W (compared to the Opteron 875HE’s 55 W). The mobile Merom core will have a standard-voltage version with a power consumption of 35 W and a low-voltage version of 5 W.

Above is from Wikipedia

Pipeline Depth

As mentioned earlier, the Netburst architecture adopted an unprecedented 31-stage pipeline, but it was soon discovered that pipeline depth can be excessive; in the Core architecture, the pipeline depth is 14.

Superscalar Support

In the P6 microarchitecture, a 3-issue superscalar pipeline is supported. In the 7th-generation Netburst microarchitecture, possibly because the pipeline was too long to make multi-issue easy, it regressed to 2-issue. The 8th-generation Core microarchitecture, being redesigned, also reduced the pipeline length to a maximum of 14 stages, and its superscalar level was further improved to 4-issue.

Memory System

The Core microarchitecture supports separated L1 instruction cache and data cache, each 32 KB. Each core has its own dedicated set. The L2 cache is shared, and there is no L3 cache.

Microcode

Starting with the Core microarchitecture, Intel CPUs began using micro-ops; after fetch and decode, each x86 CISC instruction is translated into one or more RISC instructions. In the second half of the pipeline, some RISC CPU techniques can be leveraged to improve instruction execution efficiency.

As can be seen from the architecture diagram above, the decode unit consists of three simple decoders and one complex decoder. The simple decoders output 1 micro-op, while the complex decoder outputs 4 micro-ops.

The bad news is that in this generation of microarchitecture, micro-ops do not support 64-bit instructions.

SSE3

In the previous-generation microarchitecture, 128-bit SSE instructions required 2 cycles; now only one cycle is needed.

Enhanced Intel SpeedStep Technology

This has existed before: the initial operating frequency is very low, and the workload determines whether to switch to a higher frequency. This reduces power consumption.

Virtualization Technology

Virtualization technology includes CPU virtualization, memory virtualization, network virtualization, etc. In short, it provides some hardware and instructions to ensure that multiple virtual machines can share computing, storage, and network resources without affecting each other. Virtualization technology deserves its own dedicated topic.

Intel Active Management Technology (AMT, active management technology)

Intel Active Management Technology [1] is a hardware-based remote management technology and is one of Intel vPro [2] technologies. This technology primarily allows IT personnel to Discover, Heal, and Protect desktops, laptops, or servers through an OOB (out-of-band) network connection.

In simple terms, this thing is somewhat similar to the BMC system on modern servers. BMC integrates a small CPU on the motherboard, while AMT directly integrates another small CPU inside the CPU. This small CPU, or SoC, can manage your network, memory, etc. outside of user control. It sounds dangerous just hearing about it.

Hardware security expert Damien Zammit pointed out on the BoingBoing blog site [3] that Intel built a subsystem in some CPUs called the Intel Management Engine, which cannot be disabled, to run AMT. This subsystem runs inside the Intel processor and is independent of the computer’s own closed-source operating system. It can directly access the computer’s memory and create a TCP/IP server through Intel’s network interface, giving AMT remote control capability regardless of whether the computer’s own operating system has a firewall running, and even when the computer is in sleep mode it can run at extremely low power consumption. Zammit pointed out that this subsystem’s source code is closed and the system firmware is encrypted with the RAS 2048-bit algorithm, making it impossible to audit its security or determine whether it is a so-called NSA backdoor. If the system code is maliciously misused, every computer that uses an Intel processor and is connected to the Internet could allow the subsystem to become an exposed rootkit.