7th-Generation x86 Processor: Pentium 4

The Pentium II and Pentium III that followed the Pentium Pro were both based on the P6 architecture. They introduced no major functional or architectural improvements; instead, the fabrication process continued to advance and clock frequencies continued to rise, with the Pentium III eventually reaching a maximum of 1.4 GHz. It is also worth mentioning that the Pentium already had the MMX instruction set, while the Pentium III added the SSE instruction set. We will discuss these additional instruction sets in detail in a dedicated article.

7th-Generation Processor Architecture: NetBurst

The 6th-generation processor architecture was called P6. The 7th-generation processor architecture was called NetBurst, and it was first used in the Pentium 4 processor. Many processor models based on this architecture were released, with some features added or removed from each model. They spanned the years 2002–2005. Rather than describing the feature changes in every model individually, we will simply list all the new features introduced over this entire period. They included:

1. Hyper-Threading
2. SSE2/SSE3 instruction sets
3. NX bit
4. SpeedStep
5. TM2 temperature monitoring
6. Larger L2 and L3 caches
7. A pipeline of up to 31 stages
8. A maximum clock frequency of 3.6 GHz
9. A 90 nm fabrication process

Seeing a clock frequency of 3.6 GHz and a 90 nm process really makes it feel as though we have arrived in a familiar era, because today’s mainstream processors still have clock frequencies in the 3.x GHz range, while their fabrication processes are likewise measured on the scale of tens of nanometers.

The Longest Pipeline in History

The NetBurst architecture may not actually have had the longest pipeline in history, but that is essentially how textbooks describe it. In the Pentium Pro era, everyone saw the benefits of pipelining and began using pipelines extensively. Now we had a pipeline as long as 31 stages, but the results were not very good, so pipelines were later shortened again.

For discussions of why a longer pipeline is not necessarily better, see:
https://www.zhihu.com/question/20180643
And:
http://blog.jobbole.com/40844/
http://blog.csdn.net/zqm201/article/details/45558465

Hyper-Threading

每个单位时间内，一个单运行管线的CPU只能处理一个线程（操作系统：thread），以这样的单位进行，如果想要在一单位时间内处理超过一个线程是不可能的，除非是有两个CPU的实体单元。双核心技术是将两个一样的CPU放置于一个封装内（或直接将两个CPU做成一个芯片），而英特尔的HT技术是在CPU内部仅复制必要的资源、让两个线程可同时运行；在一单位时间内处理两个线程的工作，模拟实体双核心、双线程运作。

Intel自Pentium开始引入超标量、乱序运行、大量的寄存器及寄存器重命名、多指令解码器、预测运行等特性；这些特性的原理是让CPU拥有大量资源，并可以预先运行及平行运行指令，以增加指令运行效率，可是在现实中这些资源经常闲置；为了有效利用这些资源，就干脆再增加一些资源来运行第二个线程，让这些闲置资源可运行另一个线程，而且CPU只要增加少数资源就可以模拟成两个线程运作。

P4处理器需多加一个Logical CPU Pointer（逻辑处理单元）。因此P4 HT的die的面积比以往的P4增大了5%。而其余部分如ALU（整数运算单元）、FPU（浮点运算单元）、L2 Cache（二级缓存）并未增加，且是共享的。

The above content comes from Wikipedia.

As I understand it, superscalar technology allows a single CPU core to execute up to two instructions simultaneously—or even more—but superscalar technology is effective only when the instructions in a section of code have no dependencies on one another and can be executed out of order. Within a particular thread, this condition may sometimes exist and sometimes not, so superscalar technology cannot keep the ALUs fully utilized. Although preceding and subsequent instructions in a section of code within one thread may depend on one another, instructions from two different threads are independent in the vast majority of cases. So why not let a single CPU core execute two threads simultaneously?

In addition to requiring that the core have at least two ALUs, allowing a single CPU core to execute two threads simultaneously requires two sets of thread-related registers, but it does not require two sets of process-related registers.

1. Process-related, thread-independent hardware resources
   We know that address spaces are isolated from one process to another, so each process must have its own page table. For every running process, there must be a CR3 register that stores the location of its page table, along with a corresponding set of TLBs.

2. Thread-related hardware resources

A thread must have an instruction pointer, IP; a set of registers (EAX, EBX, ECX, EDX, etc.); and a stack (SP, BP).

SpeedStep

SpeedStep技术，最早用於Pentium III Mobile处理器——一种笔记本所用的移动版CPU中，使CPU能在高、低两个确定的频率间切换，而且这种切换不是即时调整的，通常设置为当用电池时降为低频，而在用交流电源时恢复到高频（全速）。由于降为低频的同时也会降低电压和功耗，一方面CPU本身耗电量减少，另一方面发热量也会减少，这样还能缩减甚至完全避免使用风扇散热，进一步的节约了用电，因此能延长电池的使用时间；另一方面在用交流电的时候又能恢复为全速工作以获得最高性能。
SpeedStep 技术的升级版本 EIST 全名為Enhanced Intel SpeedStep Technology（增强型Intel SpeedStep技术），是Intel全新的節約能源技術，最早用于Pentium M处理器，同样也是一款笔记本所用的移动版CPU。出于和AMD台式机处理器中的Cool'n'Quiet技术竞争的目的，EIST 技术现在也推广到Intel较新的台式机处理器中，目前使用这一技术的Intel台式机和移动版CPU包括Core系列、Pentium D系統（不包括805、820、915）、Pentium M系列和超线程的Pentium 4系列（不包括5XX）。
与早期的 SpeedStep 技术不同的是，增强型 SpeedStep 技术可以动态调整CPU频率，當CPU使用率低下或接近零的時候动态降低CPU的倍率，令其工作頻率下降，從而降低电压、功耗以及发热；而一旦监测到CPU使用率很高的时候，立即恢复到原始的速率工作。当然，对于移动版处理器，仍然可以设置在使用电池的时候永远不要调整到最高频率，而始终维持在次高或者最低频率工作。

The above content comes from Wikipedia.

In one sentence, it dynamically adjusts the CPU’s operating frequency according to factors such as CPU utilization, CPU temperature, and battery level in order to save power and prevent the CPU from overheating.

TM2 Temperature Monitoring

There is no need to quote Wikipedia for this one. Intel CPUs contain an internal temperature sensor that can measure CPU temperature, as well as some integrated logic that reads the temperature in hardware. If the temperature becomes too high, it sends a signal telling the motherboard to increase fan speed, reduce the CPU’s operating frequency, or cut the power.

There is nothing technologically sophisticated about this. Its benefit is that measuring the temperature inside the CPU is more accurate than measuring it with a sensor placed outside the CPU.

NX Bit

A page-table index contains a bit called the NX (No eXecution) bit, also known as the XD (eXecution Disable) bit. When this bit is set, it indicates that the data in that page cannot be executed. The bit is located at bit 63 of the page-table entry. It was introduced primarily to prevent malicious programs from writing their malicious code into a writable data segment and then modifying the instruction pointer so that it points to and executes the malicious code in that data segment.