80586—Superscalar Execution in the First-Generation Pentium

The first-generation Pentium was a fifth-generation microprocessor based on the macro-core x86 architecture, and it began shipping on March 22, 1993. It was the successor to the 486 product line. Pentium was originally supposed to be named 80586 or i586, but was later named “Pentium” (i586 is generally considered to have been used for 80586-class microprocessors manufactured by Intel’s competitors).

Superscalar Architecture

By the time CPU development reached the 486, the computational units were no longer limited to the ALU; there were other units responsible for different types of operations, such as the arithmetic logic unit (ALU), multiplier, and shifter. These units could operate independently. With only one pipeline, the CPU could decode only one instruction per clock cycle. Thus, although there were multiple units, only one could work at a time, which was very wasteful. On P5, therefore, the CPU had two pipelines and could fetch two instructions, decode two instructions, and execute two instructions simultaneously (provided that they could be assigned to different computational units).

Pentium had two data paths (pipelines), allowing it to complete more than one instruction in a single clock cycle. One pipeline (called “U”) could handle any instruction, while the other (called “V”) could handle simple integer instructions and FXCH floating-point instructions. The use of more than one pipeline was a feature of traditional RISC processor designs, and this was also among the first implementations on the x86 platform, demonstrating the possibility of combining the two technologies to create an almost “hybrid” processor.

As shown in the figure:
The Pentium processor contained two sets of instruction-fetch, decode, and address-generation units, as well as two L1 caches, each 8 KB. It also had two ALUs, which could execute two instructions simultaneously. However, it had only one floating-point unit, so if both fetched instructions were floating-point instructions, they could not be executed at the same time.

Superscalar is not hyper-threading. Hyper-threading requires a single core to have two sets of execution units as well as two sets of registers for preserving thread state. Superscalar does not have these, so it cannot execute two instructions from two different threads simultaneously; it can only execute two instructions from the same thread. The two instructions do not have to be consecutive: they can be any two instructions within a section of code that the CPU hardware determines do not depend on each other’s results. In other words, given four instructions A, B, C, and D, the CPU must be able to determine that the execution of C does not depend on the results of A or B. C can then be computed on another ALU before B without affecting the program’s final result. In this case, A and C can be executed simultaneously. This process of rearranging the instruction execution order is called out-of-order execution. Out-of-order execution generally requires a component called a ROB, or reorder buffer—a buffer that analyzes how instructions can be reordered. However, no ROB is shown in the figure above. I strongly suspect that the ROM control unit shown there is a drawing error and may actually be the ROB control unit.